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Figure 5-7.
SCK
SCS
SPI Read and Write Operations
SDI
0
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
SDO
Hz
SPI Write
SCK
SCS
SDI
1
A6
A5
A4
A3
A2
A1
A0
Hz
SDO
D7
D6
D5
D4
D3
D2
D1
D0
SPI Read
The first byte of a pair is the command/address byte. The most significant bit of this byte indi-
cates register read when 1 and register write when 0. The remaining seven bits of the
command/address byte indicate the address of the register to be accessed.
The second byte of the pair is the data byte. During a read operation, the SDO becomes active
and the 8-bit contents of the register are driven out MSB first. The SDO will be in high imped-
ance on either the falling edge of SCK following the LSB or the rising edge of SCS, whichever
occurs first.
SDI is a don't care during the data portion of read operations. During write operations, data is
driven into the AT73C224-x via the SDI pin, MSB first. The SDO pin will remain in high imped-
ance during write operations. Data always transitions with the falling edge of the clock and is
latched on the rising edge. The clock should return to a logic high when no transfer is in
progress.
? Continuous clocking : In normal operation, the SCK should not transition out of byte transfer
periods. However, in test mode, the SCK is used as the main clock. This implies that all data
transfers must be controlled by the assertion of the SCS pin.
? 3-wire operation : SDI and SDO can be treated as two separate lines or wired together if the
master is capable of tri-stating its output during the data-byte transfer of a read operation.
? SCK vs internal clock rates : It is very likely that the bit rate commanded by SCK will be
much higher than the internal clock (900 kHz/64) used to read and write the registers. This
implies that a minimal delay between byte transfers must be imposed to allow some time to
decode the address and actually access the physical register. It is not acceptable to sample
SCK with the internal clock.
16
AT73C224
6266A–PMAAC–08-Sep-08
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